[cse141] FAQ of lab #2 (2)

[Yuanfang HU <yhu@cs.ucsd.edu>]

CSE141L students,

Lab #2 FAQ2:

Q: When creating a new project in Xilinx, which settings should I choose?
A: You can just use the default setting in Xilinx. This setting doesn't
matter in our lab.

Q: Do I need to implement hardware for program counter and instruction
sequence?
A: No, this is for lab #3.

Q: Do I need to implement load and store instructions, how about halt
instruction?
A: For memory operations, you should implement address calculation
hardware. You don't need to worry about halt instruction in lab #2.

Q: Can the ALU have 9-bit inputs/outputs? Since I have more than 8 ALU
operations, can I use four control bits?
A: Yes, both are okey if they are needed.

Q: Can the ALU contain output flags within it?
A: Yes, you can have control bit outputs from the ALU.

Q: Do we need to do timing simulation or function simulation?
A: You need to do function simulation for each ALU instruction you have.

Q. Is there anything specific we should take note of in the timing
diagrams?
A. Yes, please make sure that after you have finished the simulation,
combine the buses of the ALU input so that it reads the values in one row
instead of having 8 bits spread across 8 rows. This will make the grading
much easier! Also, when doing this make sure that your bits are in the
right order, otherwise all your values will be wrong.

Q. Are there exceptions for turning in labs late due to printer being out
of paper in the lab?
A. No! This often happens towards the end of the due date. This is why you
should start early.


Cheers,
-Yuanfang Hu, Lab TA