|
CSE 141L Students:
Some of you used device families in Xilinx
other than xc4000 to generate your schematics for Lab #2. However, for Lab #3,
RAM and ROM components do not exist in other families. To generate
these:
on the Menu bar of the design
click on Tools->LogiBLOX Module
Generator
click on Setup
choosed the Device Family Tab
change it to xc4000e
click OK
now the ROM and RAM components should become
available. I tested the memory units with some simple gate logic from the other
device families and all seemed to be working well.
Another note: in editting your memory units,
be sure that all your data and mem addresses are in
hex.
-Jen (CSE 141L
tutor)
|