[cse141] Lab 4 Announcements

[jchai@ucsd.edu]

CSE141L Students,

Here are a few announcements/clarifications that resulted from the lab 
lecture this past Tuesday. 

1. In finding the longest path in your current CPU design, you may use the 
Xilinx Tools if you want. However, you still need to provide analysis of 
this path using the description provided in the lab (counting logic gates).

2. In counting the number of cycles it takes to execute your programs with 
your new pipelined designs, write out all the instructions (statically! DO 
NOT UNROLL ALL YOUR LOOPS!) and indicate next to each instruction which 
cycle it will begin execution (this will help indicate where the 
stalls/bubbles in your pipeline will be). You will need to provide some 
analysis on how stalls/bubbles effect your loops when they are taken and 
not taken.

3. If you are planning on doing the extra credit portion, use the data map 
from Lab 3 to do the simulations.

Good luck!
Jen.


--
This message was sent using Sake Mail, a web-based email tool from
Endymion Corporation.  http://www.endymion.com/products/sake